1. Field of the Invention
The present invention relates to a cascade delta-sigma modulation quantizer, and more particularly to a cascade delta-sigma modulator capable of obtaining full-scale output by preventing S/N ratio reduction caused in the vicinity of the input full-scale range.
2. Prior Art
A/D converter circuits incorporating delta-sigma modulators have been known conventionally. FIG. 3 shows an A/D converter circuit incorporating a single-stage delta-sigma modulator in accordance with a prior art. A delta-sigma modulator 1 comprises an integration circuit 2 to which an analog input signal and a feedback reference voltage (positive voltage VREF+ or negative voltage VREF−) are input, a quantizer 3 for quantizing the output of the integration circuit 2 into a digital signal, and a DA converter 4 for generating the above-mentioned feedback reference voltage from the digital output of the quantizer 3. The above-mentioned positive and negative reference voltages are usually set so as to be the same as the specified positive/negative maximum voltages of the analog input signal.
The output signal of the delta-sigma modulator 1 is input to a digital decimation filter 5 as digital codes. A low-frequency component corresponding to the analog input signal component is extracted and converted into digital data having a predetermined bit number.
In order to reduce noise in the output digital signal of this type of A/D converter, a scaling system is proposed wherein the gain of the delta-sigma modulator 1 is limited to 1/A (A is any given numeric value larger than 1), and gain A is given to the decimation filter 5 by using its impulse response coefficient (refer to U.S. Pat. No. 4,851,841).
This is resulted from the consideration that the A/D converter circuit shown in FIG. 3 has a noise characteristic shown in FIG. 5 depending on the level of the analog input signal. In FIG. 5, curve A indicates the characteristic of noise in the digital output depending on the level of the analog input signal in the single-stage delta-sigma modulator. In addition, curve B indicates the characteristic of noise in the digital output depending on the level of the analog input signal in a cascade delta-sigma modulator.
As shown in FIG. 5, the A/D converter circuit shown in FIG. 3 gets into an “overload” state wherein the noise in the digital output increases when the level of the analog input signal is close to its full-scale level, that is, the feedback reference voltage of the delta-sigma modulator 1.
Hence, the feedback reference voltage is set so that each of the specified positive/negative maximum voltages of the analog input signal is 1/A (for example, 1/A=0.7) of the positive/negative feedback reference voltages. Hence, the gain of the delta-sigma modulator 1 is limited to 1/A. However, gain A (referred to as a scaling coefficient) is given to the decimation filter 5 provided at the later stage, whereby the gain limited by the delta-sigma modulator is compensated. Since this kind of scaling is carried out, the noise can be reduced effectively. The higher the order of the integrator incorporated in a delta-sigma modulator, the lower the input level at which overload occurs. For this reason, it is necessary to increase the scaling coefficient.
In addition, in delta-sigma modulators of recent years, a configuration referred to as a cascade configuration is used frequently to make an attempt for minimizing overload as shown in FIG. 5. A cascade delta-sigma modulator is defined as a modulator having two or more delta-sigma modulator stages comprising a first-order or multi-order integrator and cascade-connected with one another, as disclosed in Japanese Laid-open Patent Application Sho 61-177818 (the patent publication of unexamined application, the number of which is cited herein, is incorporated in this specification by reference).
FIG. 4 is a block diagram showing an A/D converter incorporating a cascade delta-sigma modulator. A cascade delta-sigma modulator 7 comprises a first-stage delta-sigma modulation quantization loop 11, second-stage to nth-stage (n is an integer of 3 or more) delta-sigma modulation quantization loops, that is, second-stage and subsequent sigma modulation quantization loops 12 to 1n, cascade-connected to the first-stage delta-sigma modulation quantization loop 11, and a noise reduction circuit 6 for reducing noise by synthesizing the outputs of the first-stage to nth-stage delta-sigma modulation quantization loops 11 to 1n. A two-stage configuration comprising the first-stage and second-stage delta-sigma modulation quantization loops may also be used. In other words, the number of the second-stage and subsequent sigma modulation quantization loops cascade-connected to the first-stage delta-sigma modulation quantization loop may be one or more.
The first-stage delta-sigma modulation quantization loop 11 comprises an integration circuit 2 to which an external analog input signal, the positive/negative maximum voltages of which are specified, and a feedback reference voltage are input, a local quantizer 3 for quantizing the output of the integration circuit 2 into a digital signal, and a DA converter 4 for generating the above-mentioned feedback reference voltage from the digital output of the local quantizer 3. This loop is used as a unit stage.
Each of the second-stage and subsequent sigma modulation quantization loops 12 to 1n comprises the integration circuit 2, the local quantizer 3 and the DA converter 4, just as in the case of the first-stage delta-sigma modulation quantization loop 11.
However, each of the analog signals input to the second-stage and subsequent sigma modulation quantization loops 12 to in is the difference signal between the input of the local quantizer 3 of the previous-stage delta-sigma modulation quantization loop and the output of the DA converter 4 of the previous-stage delta-sigma modulation quantization loop. This difference signal corresponds to the quantization error generated by the local quantizer 3 of the previous-stage delta-sigma modulation quantization loop. Furthermore, the local quantizer 3 in each of the second-stage and subsequent sigma modulation quantization loops 12 to in quantizes the analog input signal formed of the quantization error.
For example, the difference signal between the input of the local quantizer 3 of the first-stage delta-sigma modulation quantization loop 11 and the output of the DA converter 4 of the first-stage delta-sigma modulation quantization loop 11 is input to the integration circuit 2 of the second-stage delta-sigma modulation quantization loop 12 as an analog signal. This difference signal corresponds to the quantization error generated by the local quantizer 3 of the first-stage delta-sigma modulation quantization loop 11. Furthermore, the local quantizer 3 of the second-stage delta-sigma modulation quantization loop 12 quantizes the analog input signal formed of the quantization error.
An analog signal similar to that described above is input from the second-stage delta-sigma modulation quantization loop 12 to the third-stage delta-sigma modulation quantization loop 13, and an operation similar to that of the second-stage delta-sigma modulation quantization loop 12 is carried out. Operations in the fourth-stage and subsequent loops are similar to that of the third-stage loop.
The noise reduction circuit 6 has a configuration wherein the signal obtained by delaying the output signal of the local quantizer 3 of each of the delta-sigma modulation quantization loops 11 to 1(n−1) is added to the signal obtained by differentiating the output signal of the local quantizer 3 of each of the next-stage delta-sigma modulation quantization loops 12 to 1n, and the signal obtained by the addition is used as the output signal of the cascade delta-sigma modulator 7.
More specifically, in the case of a two-stage configuration, for example, in the noise reduction circuit 6, the signal obtained by delaying the output signal of the local quantizer 3 of the first delta-sigma modulation quantization loop 11 is added to the signal obtained by differentiating the output signal of the local quantizer 3 of the second-stage delta-sigma modulation quantization loop 12, and the signal obtained by the addition is used as the output signal of the cascade delta-sigma modulator 7.
In the case when the third-stage delta-sigma modulation quantization loop 13 is present, the signal obtained by delaying the output signal of the local quantizer 3 of the second delta-sigma modulation quantization loop 12 is added to the signal obtained by differentiating the output signal of the local quantizer 3 of the third-stage delta-sigma modulation quantization loop 13, and the signal obtained by the addition is used instead of the output signal of the local quantizer 3 of the second-stage delta-sigma modulation quantization loop 12, in the above-mentioned operation, whereby the output signal of the cascade delta-sigma modulator 7 is calculated. Similar operations are carried out in the case when the fourth and subsequent delta-sigma modulation quantization loops are present.
With this configuration, quantization noise generated in each of the delta-sigma modulation quantization loops 11 to 1(n−1) can be canceled by the next-stage delta-sigma modulation quantization loops 12 to 1n respectively corresponding thereto.
The output signal of the cascade delta-sigma modulator 7 is input to the digital decimation filter 5 as digital codes. In the digital decimation filter 5, a low-frequency component corresponding to the analog input signal component is extracted and converted into digital data having a predetermined bit number.
FIG. 6 is a block diagram showing an A/D converter incorporating a 1:2 cascade delta-sigma modulator as a specific configuration example of the cascade delta-sigma modulator shown in FIG. 4. A 1:2 cascade delta-sigma modulator 51 comprises a first-stage delta-sigma modulation quantization loop 52 provided with a first-order integration circuit 54, a second-stage delta-sigma modulation quantization loop 53 provided with a second-order integration circuit 55, and a noise reduction circuit 56.
The first-stage delta-sigma modulation quantization loop 52 comprises an integrator 61, a local quantizer 62, and a 1-bit DA converter 63. The signal obtained by passing the feedback reference voltage generated by the DA converter 63 through an amplifier 64 is subtracted from an external analog input signal by an adder/subtracter 65, and the signal obtained by the subtraction is input to the integrator 61. The local quantizer 62 quantizes the output of the integrator 61 into a 1-bit digital signal. The DA converter 63 generates the above-mentioned feedback reference voltage from the digital output Y1 of the local quantizer 62. The integrator 61, the amplifier 64 and the adder/subtracter 65 form the integration circuit 54.
The second-stage delta-sigma modulation quantization loop 53 comprises an integrator 71, an integrator 72, a local quantizer 73, and a 1-bit DA converter 74. The signal obtained by passing the feedback reference voltage generated by the DA converter 74 through an amplifier 75 is subtracted by an adder/subtracter 77 from the difference signal between the input of the local quantizer 62 and the output of the DA converter 63 of the first-stage delta-sigma modulation quantization loop 52, that is, the quantization error Q1 generated by the local quantizer 62 of the first-stage delta-sigma modulation quantization loop 52, and the signal obtained by the subtraction is input to the integrator 71. The signal obtained by passing the feedback reference voltage generated by the DA converter 74 through an amplifier 76 is subtracted from the output of the integrator 71 by an adder/subtracter 78, and the signal obtained by the subtraction is input to the integrator 72. The local quantizer 73 quantizes the output of the integrator 72 into a 1-bit digital signal. The DA converter 74 generates the above-mentioned feedback reference voltage from the digital output Y2 of the local quantizer 73. The integrators 71 and 72, the amplifiers 75 and 76 and the adders/subtracters 77 and 78 form the integration circuit 55.
Both the scaling coefficients of the above-mentioned first-stage and second-stage delta-sigma modulation quantization loops 52 and 53 are set at A (A is any given numeric value larger than 1); in other words, they are set at the same value. In the first-stage and second-stage delta-sigma modulation quantization loops 52 and 53, the gain is limited to 1/A. The scaling coefficient A is herein attained by setting the level of the feedback reference voltage so that the specified positive/negative maximum voltages of the analog input signal are 1/A of the positive/negative feedback reference voltages, respectively, as described above.
In FIG. 6, reference code Q1 designates the quantization error generated across the local quantizer 62, and reference code Q2 designates the quantization error generated across the local quantizer 73. Reference code N designates analog noise, other than quantization noise, such as noise mixed in the analog input signal and input-converted thermal noise.
The noise reduction circuit 56 is connected so as to receive the output signals Y1 and Y2 of the delta-sigma modulation quantization loops 52 and 53, respectively. A delay device 81 is connected so as to receive the output Y1 and operates to delay the data of the output Y1 with respect to the data of the output Y2 in terms of time when the data of the output Y1 is sent to an adder 83. A differentiator 82 is formed of a digital differentiator that carries out differentiation in accordance with the known prior art method. The output of the digital differentiator 82 is added to the output of the delay device 81 by the adder 83, and the signal obtained by the addition becomes the output signal Y of the 1:2 cascade delta-sigma modulator 51. This output signal Y is given to a digital decimation filter 57 as digital codes.
As a result, when it is assumed that the coefficients g1 and g2 of the amplifiers 64 and 75 are set at 1 and that the coefficient g3 of the amplifier 76 is set at 2, for example, the output Y of the 1:2 cascade delta-sigma modulator 51 can be represented by the following transfer function:Y1=Vin/A+N+(1−Z−1)Q1  (1)
Y2=−Q1+(1−Z−1)2Q2  (2)                     Y        =                              Y1            +                          Y2              ·                              (                                  1                  -                                      Z                                          -                      1                                                                      )                                              ⁢                                          ⁢                                           =                                    Vin              /              A                        +            N            +                                                            (                                      1                    -                                          Z                                              -                        1                                                                              )                                3                            ⁢              Q2                                                          (        3        )            
The output Dout of the digital decimation filter 57 is represented by the following function:                     Dout        =                              Y            ·            A                    ⁢                                          ⁢                                           =                      Vin            +                                          [                                  N                  +                                                                                    (                                                  1                          -                                                      Z                                                          -                              1                                                                                                      )                                            3                                        ⁢                    Q2                                                  ]                            ·              A                                                          (        4        )            
Hence, S/N ratio deterioration at the time of the maximum signal input can be prevented by the gain scaling. However, the analog noise component N and the quantization noise component (1−Z−1)3Q2 are multiplied by A, whereby the S/N ratio is sacrificed.
In order that a delta-sigma modulator satisfying a high S/N ratio of 90 dB or more is attained, the S/N characteristic is required to be improved further. In this kind of high-performance delta-sigma modulator, analog noise rather than quantization noise is dominant in the signal frequency range. This is based on the following reason. In the case of the quantization noise component in the signal frequency range, the theoretical performance of an S/N ratio of 100 dB or more can be attained by increasing the order of quantization. However, in the case of the analog noise component, it is difficult to attain an S/N ratio of 90 dB or more. Hence, for the improvement of the S/N ratio, it is important to solve the problem of how to prevent the increase in the analog noise component owing to scaling.
Furthermore, as another problem, in the conventional gain scaling, the modulator is required to be designed in combination with the decimation filter provided in the later stage, resulting in a defect of low freedom of design.